A New Efficient and Reliable Dynamically Reconfigurable Network-on-Chip

We present a new reliable Network-on-Chip (NoC) suitable for Dynamically Reconfigurable Multiprocessors on Chip systems. The proposed NoC is based on routers performing online error detection of routing algorithm and data packet errors. Our work focuses on adaptive routing algorithms which allow to bypass faulty components or processor elements dynamically implemented inside the network. The proposed routing error detection mechanism allows to distinguish routing errors from bypasses of faulty components. The new router architecture is based on additional diagonal state indications and specific logic blocks allowing the reliable operation of the NoC. The main originality in the proposed NoC is that only the permanently faulty parts of the routers are disconnected. Therefore, our approach maintains a high run time throughput in the NoC without data packet loss thanks to a self-loopback mechanism inside each router. [Read More]