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BINUS 38th
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  • MRAM Tech Startup Says Its Device Solves DRAM’s Row Hammer Vulnerability

MRAM Tech Startup Says Its Device Solves DRAM’s Row Hammer Vulnerability

04 Sep 2020
  • Articles

Spin Memory’s vertical gate-all-around transistor could shrink MRAM and other embedded memories

By Samuel K. Moore

Fremont, Calif.-based magnetic RAM startup, Spin Memory, says it has developed a transistor that allows MRAM and resistive RAM to be scaled down considerably. According to the company, the device could also defeat a stubborn security vulnerability in DRAM called Row Hammer.

Spin Memory calls the device the “Universal Selector.” In a memory cell, the selector is the transistor used to access the memory element—a magnetic tunnel junction in MRAM, a resistive material in RRAM, and a capacitor in DRAM. These are usually built into the body of the silicon, with the memory element constructed above them. Making the selector smaller and simplifying the layout of interconnects that contact it, leads to more compact memory cells.

Essentially, transistors are built horizontal to the plane of the silicon. When the device is on, current flows through a channel region between a source and drain. The Universal Selector tilts that geometry 90 degrees. The source is at bottom attached to a conductor buried in the silicon, the channel region is a vertical silicon pillar, and the drain is on top. The gate, the part of the device that controls the flow of charge, surrounds the channel region ion all sides.

Such vertical gate-all-around devices are similar to those used to make today’s multilayer NAND flash storage chips. But Spin Memory’s devices span only one layer and are tuned to operate at much lower voltages.

According to the company, the vertical device would improve DRAM array density by 20-35% and allow manufacturers to pack up to five times more MRAM or RRAM memory into the same area.

The selector is part of a trio of inventions Spin Memory is developing to boost MRAM’s adoption. The other two are an improved magnetic tunnel junction, and a circuit design that boosts MRAM’s endurance and read and write speeds, as well as eliminating sources of error. The combination, according to Jeff Lewis, senior vice president of product development, would bring MRAM to a level of performance on par with SRAM, the superfast memory embedded in today’s CPUs and other processors. [READ MORE]

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