In the quest to keep Moore’s Law going, you might imagine wanting to shrink transistors until the smallest part was just an atom thick. Unfortunately, that won’t work for silicon. Its semiconducting properties require a third dimension. But there is a class of materials that act as semiconductors even though they are two-dimensional. And new results from some of the biggest chip companies and research institutions show that these 2D semiconductors could be a good path forward once silicon’s limits are reached.

In work presented this week at IEEE International Electron Devices Meeting, in San Francisco, researchers at Intel, Stanford, and TSMC presented separate solutions to one of the most vexing barriers to making 2D transistors: sharp spikes of resistance at the places where the semiconductor meets metal contacts. Meanwhile, engineers at imec showed both how they’re clearing a path to commercial-grade manufacturing processes and demonstrating just how small future 2D transistors might be. And researchers in Beijing and Wuhan have constructed the 2D equivalents of the most advanced types of silicon devices.

“Silicon has reached its limit,” says Krishna Saraswat, a professor of electrical engineering at Stanford University. “People claim that Moore’s Law is over, but in my opinion that’s not the case. Moore’s Law can continue by going in the 3rd dimension.” For that, you need 2D semiconductors or something like them, says Saraswat, who collaborates with Stanford professors Eric Pop and H.-S. Philip Wong on 3D chips. Because of their potential to scale down to small size and relatively low processing temperatures, 2D semiconductors could be built in multiple layers.

2D semiconductors belong to a class of materials called transition metal dichalcogenides. Among them, the best studied is molybdenum disulfide. Electrons should theoretically zip through tungsten disulfide, another such 2D material, more quickly than MoS2. But in experiments at Intel, MoS2 devices were superior.

Perhaps the biggest obstacle 2D semiconductors face is making low-resistance connections to them. The problem is called “Fermi-level pinning”, but what it means is that a mismatch between the electron energies of the metal contact and the semiconductor creates a high-resistance barrier to the flow of current. This Schottky barrier is created because electrons near the interface flow into the lower-energy material, leaving a charge-depleted area that resists current. The aim now is to make that region so insignificant that electrons can just tunnel across it without much effort.

Rival chipmakers TSMC and Intel separately hit on a different solution—antimony

Aravindh Kumar, a student of Saraswat’s, came up with one of a pair of solutions to the problem that were reported at IEDM. In prior research, gold had been the contact of choice for forming transistors with MoS2. But depositing gold and other high-melting-point metals damages the MoS2, making the barrier problem worse. So Kumar experimented with indium and tin, which have melting points in the low hundreds of degrees C. [READ MORE]